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Silicon Labs /SiM3_NRND /SIM3C167_B /PBCFG_0 /XBAR0L

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Interpret as XBAR0L

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DISABLED)USART0EN 0 (DISABLED)USART0FCEN 0 (DISABLED)USART0CEN 0 (DISABLED)SPI0EN 0 (DISABLED)SPI0NSSEN 0 (DISABLED)USART1EN 0 (DISABLED)USART1FCEN 0 (DISABLED)USART1CEN 0 (NONE)EPCA0EN 0 (NONE)PCA0EN 0 (NONE)PCA1EN 0 (DISABLED)EECI0EN 0 (DISABLED)ECI0EN 0 (DISABLED)ECI1EN 0 (DISABLED)I2S0TXEN 0 (DISABLED)I2C0EN 0 (DISABLED)CMP0SEN 0 (DISABLED)CMP0AEN 0 (DISABLED)CMP1SEN 0 (DISABLED)CMP1AEN 0 (DISABLED)TMR0CTEN 0 (DISABLED)TMR0EXEN 0 (DISABLED)TMR1CTEN 0 (DISABLED)TMR1EXEN

ECI1EN=DISABLED, TMR1EXEN=DISABLED, USART0FCEN=DISABLED, CMP1SEN=DISABLED, USART0CEN=DISABLED, TMR0CTEN=DISABLED, SPI0NSSEN=DISABLED, CMP1AEN=DISABLED, CMP0SEN=DISABLED, PCA1EN=NONE, I2C0EN=DISABLED, EECI0EN=DISABLED, CMP0AEN=DISABLED, PCA0EN=NONE, ECI0EN=DISABLED, USART1FCEN=DISABLED, I2S0TXEN=DISABLED, USART1EN=DISABLED, TMR1CTEN=DISABLED, TMR0EXEN=DISABLED, USART1CEN=DISABLED, USART0EN=DISABLED, SPI0EN=DISABLED, EPCA0EN=NONE

Description

Crossbar 0 Control (Low)

Fields

USART0EN

USART0 Enable.

0 (DISABLED): Disable USART0 RX and TX on Crossbar 0.

1 (ENABLED): Enable USART0 RX and TX on Crossbar 0.
USART0FCEN

USART0 Flow Control Enable.

0 (DISABLED): Disable USART0 flow control on Crossbar 0.

1 (ENABLED): Enable USART0 flow control on Crossbar 0.
USART0CEN

USART0 Clock Signal Enable.

0 (DISABLED): Disable USART0 clock on Crossbar 0.

1 (ENABLED): Enable USART0 clock on Crossbar 0.
SPI0EN

SPI0 Enable.

0 (DISABLED): Disable SPI0 SCK, MISO, and MOSI on Crossbar 0.

1 (ENABLED): Enable SPI0 SCK, MISO, and MOSI on Crossbar 0.
SPI0NSSEN

SPI0 NSS Pin Enable.

0 (DISABLED): Disable SPI0 NSS on Crossbar 0.

1 (ENABLED): Enable SPI0 NSS on Crossbar 0.
USART1EN

USART1 Enable.

0 (DISABLED): Disable USART1 RX and TX on Crossbar 0.

1 (ENABLED): Enable USART1 RX and TX on Crossbar 0.
USART1FCEN

USART1 Flow Control Enable.

0 (DISABLED): Disable USART1 flow control on Crossbar 0.

1 (ENABLED): Enable USART1 flow control on Crossbar 0.
USART1CEN

USART1 Clock Signal Enable.

0 (DISABLED): Disable USART1 clock on Crossbar 0.

1 (ENABLED): Enable USART1 clock on Crossbar 0.
EPCA0EN

EPCA0 Channel Enable.

0 (NONE): Disable all EPCA0 channels on Crossbar 0.

1 (STD_CEX0): Enable EPCA0 STD_CEX0 on Crossbar 0.

2 (STD_CEX0_1): Enable EPCA0 STD_CEX0 and STD_CEX1 on Crossbar 0.

3 (STD_CEX0_2): Enable EPCA0 STD_CEX0, STD_CEX1, and STD_CEX2 on Crossbar 0.

4 (STD_CEX0_3): Enable EPCA0 STD_CEX0, STD_CEX1, STD_CEX2, and STD_CEX3 on Crossbar 0.

5 (STD_CEX0_4): Enable EPCA0 STD_CEX0, STD_CEX1, STD_CEX2, STD_CEX3, and STD_CEX4 on Crossbar 0.

6 (STD_CEX0_5): Enable EPCA0 STD_CEX0, STD_CEX1, STD_CEX2, STD_CEX3, STD_CEX4, and STD_CEX5 on Crossbar 0.
PCA0EN

PCA0 Channel Enable.

0 (NONE): Disable all PCA0 channels on Crossbar 0.

1 (CEX0): Enable PCA0 CEX0 on Crossbar 0.

3 (CEX0_1): Enable PCA0 CEX0 and CEX1 on Crossbar 0.
PCA1EN

PCA1 Channel Enable.

0 (NONE): Disable all PCA1 channels on Crossbar 0.

1 (CEX0): Enable PCA1 CEX0 on Crossbar 0.

3 (CEX0_1): Enable PCA1 CEX0 and CEX1 on Crossbar 0.
EECI0EN

EPCA0 ECI Enable.

0 (DISABLED): Disable EPCA0 ECI on Crossbar 0.

1 (ENABLED): Enable EPCA0 ECI on Crossbar 0.
ECI0EN

PCA0 ECI Enable.

0 (DISABLED): Disable PCA0 ECI on Crossbar 0.

1 (ENABLED): Enable PCA0 ECI on Crossbar 0.
ECI1EN

PCA1 ECI Enable.

0 (DISABLED): Disable PCA1 ECI on Crossbar 0.

1 (ENABLED): Enable PCA1 ECI on Crossbar 0.
I2S0TXEN

I2S0 TX Enable.

0 (DISABLED): Disable I2S0 TX on Crossbar 0.

1 (ENABLED): Enable I2S0 TX on Crossbar 0.
I2C0EN

I2C0 Enable.

0 (DISABLED): Disable I2C0 SDA and SCL on Crossbar 0.

1 (ENABLED): Enable I2C0 SDA and SCL on Crossbar 0.
CMP0SEN

Comparator 0 Synchronous Output (CMP0S) Enable.

0 (DISABLED): Disable Comparator 0 Synchronous Output (CMP0S) on Crossbar 0.

1 (ENABLED): Enable Comparator 0 Synchronous Output (CMP0S) on Crossbar 0.
CMP0AEN

Comparator 0 Asynchronous Output (CMP0A) Enable.

0 (DISABLED): Disable Comparator 0 Asynchronous Output (CMP0A) on Crossbar 0.

1 (ENABLED): Enable Comparator 0 Asynchronous Output (CMP0A) on Crossbar 0.
CMP1SEN

Comparator 1 Synchronous Output (CMP1S) Enable.

0 (DISABLED): Disable Comparator 1 Synchronous Output (CMP1S) on Crossbar 0.

1 (ENABLED): Enable Comparator 1 Synchronous Output (CMP1S) on Crossbar 0.
CMP1AEN

Comparator 1 Asynchronous Output (CMP1A) Enable.

0 (DISABLED): Disable Comparator 1 Asynchronous Output (CMP1A) on Crossbar 0.

1 (ENABLED): Enable Comparator 1 Asynchronous Output (CMP1A) on Crossbar 0.
TMR0CTEN

TIMER0 T0CT Enable.

0 (DISABLED): Disable TIMER0 CT on Crossbar 0.

1 (ENABLED): Enable TIMER0 CT on Crossbar 0.
TMR0EXEN

TIMER0 T0EX Enable.

0 (DISABLED): Disable TIMER0 EX on Crossbar 0.

1 (ENABLED): Enable TIMER0 EX on Crossbar 0.
TMR1CTEN

TIMER1 T1CT Enable.

0 (DISABLED): Disable TIMER1 CT on Crossbar 0.

1 (ENABLED): Enable TIMER1 CT on Crossbar 0.
TMR1EXEN

TIMER1 T1EX Enable.

0 (DISABLED): Disable TIMER1 EX on Crossbar 0.

1 (ENABLED): Enable TIMER1 EX on Crossbar 0.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data